System-on-a-chip (SOC) processors generally go through automatic test pattern generation (ATPG) testing after manufacturing to test for failures in the design and manufacturing process of the device. One type of ATPG testing is known as delay fault testing. Delay fault testing provides a test pattern to a SOC processor under test and determines whether the SOC device meets the expected timing analysis as the test pattern is propagated through the device.
Because most testers cannot produce clock speeds at the same high frequency as modern SOC processors, many testers utilize the internal clock generated by the processor to perform the at-speed testing of the processor. As a result, delay fault testing of high-speed SOC processor devices by typical ATPG testers has proven particularly difficult.